[Libre-soc-bugs] [Bug 724] Determine required memory compiler developments

[bugzilla-daemon at libre-soc.org]

https://bugs.libre-soc.org/show_bug.cgi?id=724

--- Comment #17 from Staf Verhaegen <staf at fibraservi.eu> ---
I would like to provide simulation model for a dual port SRAM + nmigen wrapper
for 1WxR blocks.
Is there a good place somewhere in the repos where I can do that ? Or should I
provide new repo ?

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