[Libre-soc-bugs] [Bug 762] Peripheral Pin Muxing Development

[bugzilla-daemon at libre-soc.org]

https://bugs.libre-soc.org/show_bug.cgi?id=762

--- Comment #14 from Andrey Miroshnikov <andrey at technepisteme.xyz> ---
Currently trying to figure out a connectivity problem for the 1-bit gpio pinmux
block (no jtag yet).
The problem is that the top-level WB bus signals are not appearing in gtkwave
trace list, and driving these signals in the sim does not affect the GPIO block
internal signals.

https://git.libre-soc.org/?p=pinmux.git;a=blob;f=src/spec/pinmux.py;h=fda23c6a7fef6b7b78f2d0b8d8edf63dfca79f0b;hb=9c35433c10860bfe85147f8f1baccd2fe3a5c915
Lines 36-41 show a top-level creation of the WB bus record.
Lines 70-80 show the connection of the top-level WB bus to the GPIO block WB
bus.
I checked the direction, should be right. In the test code, I'm just setting
the address and data signals (lines 203-204), however gtkwave does not show any
signal transitions.
Checking yosys show top, I saw that the top-level WB signals were being
connected to the GPIO block.

Have I missed something nmigen related? I haven't connected multiple blocks
like this before, so I probably missed some boiler plate code hahaha

The __iter__ definition has the top-level signals included for export.

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