[Libre-soc-bugs] [Bug 762] Peripheral Pin Muxing Development

[bugzilla-daemon at libre-soc.org]

https://bugs.libre-soc.org/show_bug.cgi?id=762

--- Comment #15 from Luke Kenneth Casson Leighton <lkcl at lkcl.net> ---
(In reply to Andrey Miroshnikov from comment #14)
> Currently trying to figure out a connectivity problem for the 1-bit gpio
> pinmux block (no jtag yet).
> The problem is that the top-level WB bus signals are not appearing in
> gtkwave trace list,

yes, there are a number of possible reasons for this:
1) a bug in gtkwave, which you can compensate for by adding
   a top-level signal then assigning the whatever-bus signals
   to it
2) you've forgotten to bring it out via ports=[list,of,signals]
   in write_ilang/write_verilog
3) they're genuinely not connected and yosys has "optimised them out"

2 and 3 are sort-of related, in that if you don't explicitly tell
write_ilang()/write_verilog() what the signals are, yosys goes
"pffh you clearly didn't want that, let me just delete it for you"

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