[Libre-soc-bugs] [Bug 745] OP_TERNLOG instruction
bugzilla-daemon at libre-soc.org
bugzilla-daemon at libre-soc.org
Sat Mar 12 11:27:44 GMT 2022
https://bugs.libre-soc.org/show_bug.cgi?id=745
--- Comment #58 from Luke Kenneth Casson Leighton <lkcl at lkcl.net> ---
sorry jacob i moved OP_TERNLOG to its own
major op (to be chosen) good news is, Rc=1
is now possible. GT LE actually have partial
meaning there which is nice.
i am putting sone thought into the stranger
ternlog ops as well, the dynamic one in particular,
i would like to see a way to do FPGA emulation
without static immediates (the 8bit lut3 be a register)
also the extra space allows 3in 1out for CRs.
BT BA BB BC
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