[Libre-soc-bugs] [Bug 887] implement fmvis and 2nd-half variant

[bugzilla-daemon at libre-soc.org]

https://bugs.libre-soc.org/show_bug.cgi?id=887

--- Comment #9 from Luke Kenneth Casson Leighton <lkcl at lkcl.net> ---
fields.text:

 426     d0,d1,d2 (16:25,11:15,31)
 427         Immediate fields that are concatenated to specify a
 428         16-bit signed two's complement integer which is
 429         sign-extended to 64 bits.
 430         Formats: DX

Power ISA V3 1 spec

     d0,d1,d2 (16:25,11:15,31)


addpcis RT,D
 D ← d0||d1||d2

 213 * fmvis FRS,D
 214 
 215 Pseudo-code:
 216 
 217     bf16 <- d0 || d1 || d2
 218     fp32 <- bf16 || [0]*16
 219     FRS  <- DOUBLE(fp32)

yep that's all good, where the hell is it.

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