[Libre-soc-bugs] [Bug 887] implement fmvis and 2nd-half variant

[bugzilla-daemon at libre-soc.org]

https://bugs.libre-soc.org/show_bug.cgi?id=887

--- Comment #2 from Luke Kenneth Casson Leighton <lkcl at lkcl.net> ---
(In reply to Luke Kenneth Casson Leighton from comment #1)

> adding support for hexadecimal into svp64.py, though, no problem at all.
> it should be in theory easy to add here:
>    
> https://git.libre-soc.org/?p=openpower-isa.git;a=blob;f=src/openpower/sv/
> trans/svp64.py;hb=HEAD#l48

nope, here:

https://git.libre-soc.org/?p=openpower-isa.git;a=commitdiff;h=8b17162fd38e163f522729efe3c863b04d0884a0

so that exact same place would be where conversion from float to
number would be performed, except it's more complex in the case
of fmvis because of the truncation (taking the top 16 bits of
a FP number).  that can be "hack-fixed" by adding in the instruction
asmcode as a 2nd argument to to_number() :)

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