[Libre-soc-bugs] [Bug 855] add libre-soc to kestrel

[bugzilla-daemon at libre-soc.org]

https://bugs.libre-soc.org/show_bug.cgi?id=855

--- Comment #30 from tpearson at raptorengineering.com ---
> bonus points if we can do an automated repro script for getting everything
> compiled-and-running (happy to have it include microwatt as an option)
> aside from anything it acts as "documentation".
> 
> if there's a 4th milestone (very short one) that could be done separately,
> or we can put someone else on it?

I don't mind putting something together, it's not too hard and I know the
commands involved.  Just expect it to be a 2 hour build cycle on a reasonably
powerful POWER workstation, and much longer on a laptop. :)

> tim did you need any TRAP pipeline changes in the end?
> or was the sorting-out on msr_o.data sufficient?
> i really want to make sure there's a unit test covering
> what you had, so need to know the input criteria: what
> was MSR when starting those 3 instructions (basically)
> mfmsr ori mtmsrd

The relevant change I made was here:

https://gitlab.raptorengineering.com/kestrel-collaboration/kestrel-litex/litex/-/blob/d86cad8308d15ce50de19684051956eaede15a46/litex/soc/cores/cpu/libresoc/core.py#L135

If for some reason that's an incorrect signal let me know.

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