[Libre-soc-bugs] [Bug 762] Peripheral Pin Muxing Development

[bugzilla-daemon at libre-soc.org]

https://bugs.libre-soc.org/show_bug.cgi?id=762

--- Comment #13 from Luke Kenneth Casson Leighton <lkcl at lkcl.net> ---
(In reply to Luke Kenneth Casson Leighton from comment #12)


> * IOConn Record will (optionally) have BankSel and PU and PD added
>   for this to work

done.

https://git.libre-soc.org/?p=c4m-jtag.git;a=summary

TAP.add_io() now has three extra parameters:

* banksel
* pullup
* pulldown

every time you now call jtag.add_io() with banksel=3, pullup=True,
pulldown=True
it will add a total of **FIVE** extra bits into the shiftregister.  three for
banksel, one for pullup, and one for pulldown.

it should be obvious that those need to be wired to the GPIO Config
as "pass-thru" stuff (core-side, pad-side) in *EXACTLY* the same way
that core/pad o/oe are wired up (because banksel, pullup and pulldown
are all outputs that go into the pad).

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