[Libre-soc-bugs] [Bug 762] Peripheral Pin Muxing Development

[bugzilla-daemon at libre-soc.org]

https://bugs.libre-soc.org/show_bug.cgi?id=762

--- Comment #12 from Luke Kenneth Casson Leighton <lkcl at lkcl.net> ---
https://libre-soc.org/pinmux/muxjtag2.png

nope, this one.

* JTAG can be removed and it would be as if nothing is changed
* JTAG can be added and if not active it would be as if it was not there
* JTAG *can* be enabled and can *FULLY* control *ALL* aspects of the
  IOPad *AND* the Muxing.
* IOConn Record will (optionally) have BankSel and PU and PD added
  for this to work
* Wishbone working on the ASIC is *NOT* required for this to work

importantly, (removing JTAG from the diagram), you can see how GPIO0
plays *TWO* roles:

1) sets banksel, pullup and pulldown
2) connects wishbone-read-writeable GPIO registers I/O/OE to Bank 0 *ONLY*

the important thing here is that if any aspect of the wishbone bus fails
at least the GPIO Muxing as well as the pullup/pulldown can be tested
over JTAG.

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