[Libre-soc-bugs] [Bug 763] Work on I/O Core Pad JTAG Tests

[bugzilla-daemon at libre-soc.org]

https://bugs.libre-soc.org/show_bug.cgi?id=763

--- Comment #7 from Luke Kenneth Casson Leighton <lkcl at lkcl.net> ---
Andrey, each Shift Register created and used in
one area for one task has absolutely nothing to
do with any other shift register.

the SR used for identity (IDBlock) has nothing
to do with the IO shift register.

the WB SR has nothing to do with theIO SR or
the ID SR.

what each piece of HDL does with each SR is entirely
up to that piece of HDL.

a module could decide to insert bits in an order related
to phases of the moon and the spot trading price of matured
smoked Edam if they wanted.

therefore the bitreversal should i feel be done by the
caller, i.e. call a explicit reverse() on the data in and
out of the test function.

if you really want to do reversal in the test function,
(which is fine btw) then
the only "safe" way to do it is to add extra named parameters
at the end of the paramlist, defaulting to values which do
NOT change the current behaviour.

so e.g. reverse=False

this is standard practice in well-maintained SQL databases and
in any code providing optional args (java, c++, python) but python
in particular has to watch out because it is interpreted.

welcome to your first experience of maintaining backwards compatibility
in software.

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