[Libre-soc-bugs] [Bug 763] Work on I/O Core Pad JTAG Tests

[bugzilla-daemon at libre-soc.org]

https://bugs.libre-soc.org/show_bug.cgi?id=763

--- Comment #6 from Luke Kenneth Casson Leighton <lkcl at lkcl.net> ---
briefly, read it again

 150         with m.Elif(self._shift):
 151             m.d.posjtag += shift_ir.eq(Cat(shift_ir[1:], self._tdi))

on the next clock of posjtag:

this is taking TDI into the top bit (MSB) and dropping the
first bit (LSB). in software:

shift_ir = shift_ir >> 1 # shift down 1 bit
shift_ir |= (tdi << len(shift_ir-1) # put TDI into MSB

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