[Libre-soc-bugs] [Bug 826] Trial run of ethmac (freecores) layout.

[bugzilla-daemon at libre-soc.org]

https://bugs.libre-soc.org/show_bug.cgi?id=826

--- Comment #2 from Jean-Paul Chaput <Jean-Paul.Chaput at lip6.fr> ---
(In reply to Jean-Paul Chaput from comment #1)

With the following script, inspired from:

   
https://git.libre-soc.org/?p=ls2.git;a=blob;f=simsoc.ys;h=a4adcefdcd7103aa29cc6578bdaf470b89e0f845;hb=0ed190756075447abdf96cb7e508e7ed92118236#l33

That is:

    yosys read_verilog  eth_clockgen.v
    yosys read_verilog  eth_cop.v
    yosys read_verilog  eth_crc.v
    yosys read_verilog  eth_fifo.v
    yosys read_verilog  eth_maccontrol.v
    yosys read_verilog  ethmac_defines.v
    yosys read_verilog  eth_macstatus.v
    yosys read_verilog  ethmac.v
    yosys read_verilog  eth_miim.v
    yosys read_verilog  eth_outputcontrol.v
    yosys read_verilog  eth_random.v
    yosys read_verilog  eth_receivecontrol.v
    yosys read_verilog  eth_registers.v
    yosys read_verilog  eth_register.v
    yosys read_verilog  eth_rxaddrcheck.v
    yosys read_verilog  eth_rxcounters.v
    yosys read_verilog  eth_rxethmac.v
    yosys read_verilog  eth_rxstatem.v
    yosys read_verilog  eth_shiftreg.v
    yosys read_verilog  eth_spram_256x32.v
    yosys read_verilog  eth_top.v
    yosys read_verilog  eth_transmitcontrol.v
    yosys read_verilog  eth_txcounters.v
    yosys read_verilog  eth_txethmac.v
    yosys read_verilog  eth_txstatem.v
    yosys read_verilog  eth_wishbone.v
    yosys read_verilog  timescale.v
    yosys hierarchy -check -top ethmac
    yosys synth            -top ethmac
    yosys memory
    yosys dfflibmap -liberty    FlexLib.lib
    yosys abc       -liberty    FlexLib.lib
    yosys clean
    yosys write_blif ethmac.blif

I can go a little further:

     Yosys 0.12+23 (git sha1 UNKNOWN, gcc 11.2.1 -fPIC -Os)

    1. Executing Verilog-2005 frontend: eth_clockgen.v
    Parsing Verilog input from `eth_clockgen.v' to AST representation.
    Generating RTLIL representation for module `\eth_clockgen'.
    Successfully finished Verilog frontend.

    2. Executing Verilog-2005 frontend: eth_cop.v
    Parsing Verilog input from `eth_cop.v' to AST representation.
    Generating RTLIL representation for module `\eth_cop'.
    eth_cop.v:0: Warning: System task `$display' outside initial block is
unsupported.
    eth_cop.v:0: Warning: System task `$display' outside initial block is
unsupported.
    eth_cop.v:0: Warning: System task `$display' outside initial block is
unsupported.
    eth_cop.v:0: Warning: System task `$display' outside initial block is
unsupported.
    eth_cop.v:0: Warning: System task `$display' outside initial block is
unsupported.
    eth_cop.v:0: Warning: System task `$display' outside initial block is
unsupported.
    eth_cop.v:0: Warning: System task `$display' outside initial block is
unsupported.
    eth_cop.v:0: Warning: System task `$display' outside initial block is
unsupported.
    eth_cop.v:0: Warning: System task `$display' outside initial block is
unsupported.
    eth_cop.v:0: Warning: System task `$display' outside initial block is
unsupported.
    eth_cop.v:0: Warning: System task `$display' outside initial block is
unsupported.
    eth_cop.v:0: ERROR: System task `$stop' outside initial block is
unsupported.


As I'm not fluent in Verilog, I cannot tell if it's a Yosys unsupported feature
or
an outright Verilog error.

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