[Libre-soc-bugs] [Bug 826] Trial run of ethmac (freecores) layout.

[bugzilla-daemon at libre-soc.org]

https://bugs.libre-soc.org/show_bug.cgi?id=826

--- Comment #1 from Jean-Paul Chaput <Jean-Paul.Chaput at lip6.fr> ---

The Verilog from Freecores/ethmac seems not be readable by Yosys.
Hang there:


     Yosys 0.12+23 (git sha1 UNKNOWN, gcc 11.2.1 -fPIC -Os)

    1. Executing Verilog-2005 frontend: ethmac.v
    Parsing Verilog input from `ethmac.v' to AST representation.
    make: *** [mk/synthesis-yosys.mk:53: ethmac.blif] Error 247

I'm setting it up as a standalone example in alliance-check-toolkit.
Do you want me to commit it right now?

There will also be likely questions about the implementation of the
FIFOs/SRAMs.

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