[Libre-soc-bugs] [Bug 826] Trial run of ethmac (freecores) layout.

[bugzilla-daemon at libre-soc.org]

https://bugs.libre-soc.org/show_bug.cgi?id=826

--- Comment #3 from Luke Kenneth Casson Leighton <lkcl at lkcl.net> ---
(In reply to Jean-Paul Chaput from comment #2)

>     eth_cop.v:0: ERROR: System task `$stop' outside initial block is
> unsupported.
> 
> 
> As I'm not fluent in Verilog, I cannot tell if it's a Yosys unsupported
> feature or
> an outright Verilog error.

https://github.com/freecores/ethmac/blob/master/rtl/verilog/eth_cop.v

it is for simulation purposes (icarus, verilator). $display and $stop
clearly will not work in an ASIC!  if you remove $stop you will
get further

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