[Libre-soc-bugs] [Bug 806] Nest should be able to run at different clock rate than main CPU

[bugzilla-daemon at libre-soc.org]

https://bugs.libre-soc.org/show_bug.cgi?id=806

--- Comment #16 from Luke Kenneth Casson Leighton <lkcl at lkcl.net> ---
not quite.  

https://git.libre-soc.org/?p=ls2.git;a=commitdiff;h=b586cc83eea22270d7914e7315565118c18fbf75

there are 4 CLKDIVFs available and 10 ECLKSYNCBs
so it is possible to a separate spi clock domain
from dram domain from hyperram domain

Info:                CLKDIVF:     1/    4    25%
Info:              ECLKSYNCB:     1/   10    10%

i'd prefer they were done one at a time (there is a project
"minimum patch" rule), let's focus on DRAM first

dram_clk_freq.  also please keep to under 80 chars

+                self.ddrphy = drs(ECP5DDRPHY(ddr_pins,
                  sys_clk_freq=memory_clk_freq))

ah... yyeah that's ok. for now.


yes, annoyingly:

-            drambone = gramWishbone(dramcore, features={'stall'})
+            drambone = gramWishbone(dramcore)

needing two Asyncs here is annoying, removing the features={stall}
is the right thing to do, it's the WBAsyncBridge that needs it.

yes:

+            self.drambone_async_br = WBAsyncBridge(
+                                         master_features={'stall'})

except stall=cyc&~ack has to be applied (i took it out
of WBAsyncBridge because it will quickly become hell:
unintended consequences)

@@ -470,6 +557,7 @@ class DDR3SoC(SoC, Elaboratable):
         self.memory_map = self._decoder.bus.memory_map

         self.clk_freq = clk_freq
+        self.memory_clk_freq = memory_clk_freq
         self.fpga = fpga

dram_clk_freq.  then, later, spi_clk_freq.  if they happen to be
made the same they can probably be aliased. TODO on that one.

y'know what? i'll pull this over.  there's great bits of code here
in easy-to-cut-paste chunks

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