[Libre-soc-bugs] [Bug 806] Nest should be able to run at different clock rate than main CPU

[bugzilla-daemon at libre-soc.org]

https://bugs.libre-soc.org/show_bug.cgi?id=806

--- Comment #15 from Luke Kenneth Casson Leighton <lkcl at lkcl.net> ---
no. has to be done in the parent because it is only the parent
that knows if the WB4-pipe is connected to a WB3-classic.

burying the WB3-to-4-botch inside the peripheral will only
make using it harder due to undocumented side-effects.


diff --git a/src/soc/bus/wb_async.py b/src/soc/bus/wb_async.py
index
60844e56055ea1e2402ee92fc9aa3754fbe41325..6775427fd300d4e2113122ba3c9e5354332458fc
100644 (file)
--- a/src/soc/bus/wb_async.py
+++ b/src/soc/bus/wb_async.py
@@ -135,16 +135,6 @@ class WBAsyncBridge(Elaboratable):
                             i_wbs_rty_i=slave_rty
                             );

-        # Synthesize STALL signal for master port
-        if hasattr(self.master_bus, "stall"):
-            comb += self.master_bus.stall.eq(self.master_bus.cyc &
~self.master_bus.ack)
-
-        # Convert incoming slave STALL signal to a format that the async
bridge understands...
-        if hasattr(self.slave_bus, "stall"):
-            comb += slave_ack.eq(self.slave_bus.ack & ~self.slave_bus.stall)
-        else:
-            comb += slave_ack.eq(self.slave_bus.ack)
-
         # Wire unused signals to 0
         comb += slave_err.eq(0)
         comb += slave_rty.eq(0)

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