[Libre-soc-bugs] [Bug 806] Nest should be able to run at different clock rate than main CPU

[bugzilla-daemon at libre-soc.org]

https://bugs.libre-soc.org/show_bug.cgi?id=806

--- Comment #14 from Luke Kenneth Casson Leighton <lkcl at lkcl.net> ---
this

   
https://git.libre-soc.org/?p=gram.git;a=commitdiff;h=dedba0951797896c4f6c44238ebffc7e4472f0f2

--- a/gram/phy/ecp5ddrphy.py
+++ b/gram/phy/ecp5ddrphy.py
@@ -40,7 +40,7 @@ class ECP5DDRPHYInit(Elaboratable):
         lock = Signal()
         lock_d = Signal()
         m.submodules += Instance("DDRDLLA",
-            i_CLK=ClockSignal("sync2x"),
+            i_CLK=ClockSignal("dramsync2x"),
             i_RST=ResetSignal("init"),
             i_UDDCNTLN=~update,
             i_FREEZE=freeze,

goes with a corresponding/matching this:

             drs = DomainRenamer({"sync": "dramsync",
                                  "sync2x": "dramsync2x"})

and this:

        # and a dram 2x sigh
        cd_dramsync2x = ClockDomain("dramsync2x", local=False)
        m.domains += cd_dramsync2x
        m.d.comb += ClockSignal("dramsync2x").eq(ClockSignal("sync2x"))

which should have bloody well been added right from the start. sigh.

anyway.

i've now added this:

https://git.libre-soc.org/?p=ls2.git;a=commitdiff;h=ea438cb108e627de4c1fd1bf96e273fc8659a2b9

+        if self.dram_clk_freq is not None:
+            self.phase2_domain(m, pll, "dramsync", self.dram_clk_freq)
+        else:
+            # alias dramsync and dramsync2x to sync and sync2x

which means that the ASyncBridge can be added with an optional
parameter, in a way that doesn't break things.

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