[Libre-soc-bugs] [Bug 199] Layout using coriolis2 main core, 180nm

[bugzilla-daemon at libre-soc.org]

https://bugs.libre-soc.org/show_bug.cgi?id=199

--- Comment #82 from Luke Kenneth Casson Leighton <lkcl at lkcl.net> ---
(In reply to Jean-Paul.Chaput from comment #81)
> I did take a quick look at your work. And, of course, I have lot of
> comments...

hooray!

>   I did notice that there are cells added obviously coming from the JTAG,
>   they must be put below the CORE level.

you mean like this?

      CHIP
        |
        +----> I/O Pad
        |
        +----> I/O Pad
        |
        +----> I/O Pad
        |
        \----> CORONA
                 |
                 +----> CORE (aka test_issuer).
                 |      ^
                 |      |
                 |      |
                 \----> jtag

actually it is more like... ahhh... i will have to draw it, it is
to do with how Staf has arranged the IO Pad JTAG testing.

give me a few minutes.

> * Why that intermediary CORONA level ? It's purpose is to isolate the
>   CORE which may be in symbolic layout from the I/O pad which usually
>   are supplied by the foundry and are real layout.
> 
> * I have a plugin that automatically generate the CHIP+CORONA level
>   from the CORE. As long as the I/O pads can be deduced from the
>   nets.

yes, i believe i have semi-worked-out how that works.  copied from
the AM2901 example, which i initially copied for experiments4

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