[Libre-soc-bugs] [Bug 199] Layout using coriolis2 main core, 180nm

[bugzilla-daemon at libre-soc.org]

https://bugs.libre-soc.org/show_bug.cgi?id=199

--- Comment #81 from Jean-Paul.Chaput at lip6.fr ---

I did take a quick look at your work. And, of course, I have lot of comments...

* First, as I'm currently re-implementing the "block" plugin for HFNS
  support and all other features, it does not support (yet) the full
  chip (with chip I/O cells).

* So, to check the full chip, you have to use the old plugin.

* That old plugin (and the future one for that matter) requires a specific
  top hierarchy:

     CHIP
       |
       +----> I/O Pad
       |
       +----> I/O Pad
       |
       +----> I/O Pad
       |
       \----> CORONA
                |
                \----> CORE (aka test_issuer + jtag).

  The chip level contains the I/O pads and the CORONA.
  The CORONA contains *one* instance of the CORE.
  The CORE contains the flat design.

  I did notice that there are cells added obviously coming from the JTAG,
  they must be put below the CORE level.

* Why that intermediary CORONA level ? It's purpose is to isolate the
  CORE which may be in symbolic layout from the I/O pad which usually
  are supplied by the foundry and are real layout.

* I have a plugin that automatically generate the CHIP+CORONA level
  from the CORE. As long as the I/O pads can be deduced from the
  nets.

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