[Libre-soc-bugs] [Bug 199] Layout using coriolis2 main core, 180nm

[bugzilla-daemon at libre-soc.org]

https://bugs.libre-soc.org/show_bug.cgi?id=199

--- Comment #83 from Jean-Paul.Chaput at lip6.fr ---
(In reply to Luke Kenneth Casson Leighton from comment #82)
> (In reply to Jean-Paul.Chaput from comment #81)
> > I did take a quick look at your work. And, of course, I have lot of
> > comments... 
> you mean like this?
> 
>       CHIP
>         |
>         +----> I/O Pad
>         |
>         +----> I/O Pad
>         |
>         +----> I/O Pad
>         |
>         \----> CORONA
>                  |
>                  +----> CORE (aka test_issuer).
>                  |      ^
>                  |      |
>                  |      |
>                  \----> jtag
>  
> actually it is more like... ahhh... i will have to draw it, it is
> to do with how Staf has arranged the IO Pad JTAG testing.

  I may have been too fast in my reading. You want to use ls180
  as the core. In that case, it is correct. Sorry.

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