[Libre-soc-bugs] [Bug 155] a PLL is needed for the SoC

[bugzilla-daemon at libre-soc.org]

https://bugs.libre-soc.org/show_bug.cgi?id=155

--- Comment #18 from Luke Kenneth Casson Leighton <lkcl at lkcl.net> ---
this is what i propose:
https://git.libre-soc.org/?p=soc.git;a=blob;f=src/soc/clock/select.py;hb=HEAD

an external suite of 3 pins allows to select from the following options:

  - 0b000 - CLK_24 (direct)
  - 0b001 - PLL / 6
  - 0b010 - PLL / 4
  - 0b011 - PLL / 3
  - 0b100 - PLL / 2
  - 0b101 - PLL
  - 0b110 - ZERO (direct driving in combination with ONE)
  - 0b111 - ONE

the default is the external 24 mhz digital drive, and it's wired
through combinatorially.

zero and one are available (note that bit zero of the "selecters"
effectively becomes the clock) for convenience, these can be
wired to a bounce-free toggle or an Embedded Controller GPIO
(e.g. STM32F)

manual clock selection through these 3 "select" wires would only be
done once the PLL is known to be stable at 300mhz.  this to be verified
by checking the PLL/6 pin (pll_48_o)

thoughts?

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