[Libre-soc-bugs] [Bug 155] a PLL is needed for the SoC

[bugzilla-daemon at libre-soc.org]

https://bugs.libre-soc.org/show_bug.cgi?id=155

--- Comment #19 from Staf Verhaegen <staf at fibraservi.eu> ---
(In reply to Luke Kenneth Casson Leighton from comment #18)
> this is what i propose:
> https://git.libre-soc.org/?p=soc.git;a=blob;f=src/soc/clock/select.py;hb=HEAD

I think you generate a circular dependency here. You should not have the
configuration register be synchronous to the clock that is generated by this
PLL.

> 
> an external suite of 3 pins allows to select from the following options:
> 
>   - 0b000 - CLK_24 (direct)
>   - 0b001 - PLL / 6
>   - 0b010 - PLL / 4
>   - 0b011 - PLL / 3
>   - 0b100 - PLL / 2
>   - 0b101 - PLL
>   - 0b110 - ZERO (direct driving in combination with ONE)
>   - 0b111 - ONE
> 
> the default is the external 24 mhz digital drive, and it's wired
> through combinatorially.
> 
> zero and one are available (note that bit zero of the "selecters"
> effectively becomes the clock) for convenience, these can be
> wired to a bounce-free toggle or an Embedded Controller GPIO
> (e.g. STM32F)
> 
> manual clock selection through these 3 "select" wires would only be
> done once the PLL is known to be stable at 300mhz.  this to be verified
> by checking the PLL/6 pin (pll_48_o)
> 
> thoughts?

It was always in the plan (in my head) to be able to bypass the PLL. Other
configuration options I would not specify as hard specs but let it come from
the  PLL design. Only supporting power of two clock division is most natural as
it allows to use just only flipflops for it, otherwise extra logic needs to be
inserted in the PLL feedback loop.

Also the division of the clock could also be made programmable through JTAG so
no extra pins are needed.

I don't think this has to be frozen at the moment for the current design
delivery as that does not include the PLL yet. We should have a meeting
somewhere mid October to finalize the package and pin allocation.

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