[Libre-soc-bugs] [Bug 155] a PLL is needed for the SoC

[bugzilla-daemon at libre-soc.org]

https://bugs.libre-soc.org/show_bug.cgi?id=155

Luke Kenneth Casson Leighton <lkcl at lkcl.net> changed:

           What    |Removed                     |Added
----------------------------------------------------------------------------
           Assignee|lkcl at lkcl.net               |dimitri.galayko at lip6.fr
             Blocks|                            |383

--- Comment #17 from Luke Kenneth Casson Leighton <lkcl at lkcl.net> ---
professor galayco,

if we are to include the 600 mhz PLL that you have developed in the 180nm SoC
it makes me nervous to have two unproven blocks connected together.

i would like us to be able to include it in a way where it can be connected and
disconnected very simply by an external pin.

also what do you think of the idea for it to be possible to independently
confirm that the PLL is functional by driving an outgoing pin on a simple
counter-divider, so that the outgoing pin does not exceed the drive speed of a
QFP pad?

something like this:

digital_clk at 24mhz -> PLL -> clk_600
clk_600 -> div2 -> clk_300
clk_300 -> div6 -> clk_48

SOC_CLK = MUX(ext_clksel,
              digital_clk at 24mhz,
              clk_48)

* clk_48 will be sent directly to an external pad.
* SOC_CLK will drive the main SoC clock
* ext_clksel will be an external pin

in this way we can independently verify the PLL by checking the clk_48 signal,
even if the SoC is nonfunctional

also we can independently verify the SoC even if the PLL is nonfunctional.

Staf does this approach run into any of the timing constraints issues you
raised?

if this is ok we can write a simple digital divider in nmigen, implementing all
of the above, where the only thing needed would be the 300mhz output from the
PLL.

(you would not need to write the 6x digital divider, professor, we can do it)


Referenced Bugs:

https://bugs.libre-soc.org/show_bug.cgi?id=383
[Bug 383] Complete first functional POWER9 Core
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