[Libre-soc-bugs] [Bug 199] Layout using coriolis2 main core, 180nm

[bugzilla-daemon at libre-soc.org]

https://bugs.libre-soc.org/show_bug.cgi?id=199

--- Comment #70 from Luke Kenneth Casson Leighton <lkcl at lkcl.net> ---
i added an experimental option to yosys to disable "memory_map" and it
resulted in this:

  File "/home/lkcl/alliance-check-toolkit/bin/blif2vst.py", line 67, in
<module>
    cell = CRL.Blif.load( options.cellName )
hurricane.HurricaneError: [ERROR] No .model or cell named <$mem> has been
found.

which i am sure is a "good thing" really.  of course... now that model
for <$mem> is actually needed, how can it be created? what do they look like?

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