[Libre-soc-bugs] [Bug 199] Layout using coriolis2 main core, 180nm

[bugzilla-daemon at libre-soc.org]

https://bugs.libre-soc.org/show_bug.cgi?id=199

--- Comment #71 from Luke Kenneth Casson Leighton <lkcl at lkcl.net> ---
     - <Box 0l 0l 18300l 18300l>
     - GCell grid: [366x366]
  o  Converting <ls180> into Coloquinte.

finally corrected enough errors to have the layout - including
litex peripherals - start compiling.

i cut out the litex BIOS as a ROM and made the SRAM only 512 bytes.
this is enough to not trigger yosys to go "mental" with the whole
SRAM-is-actually-DFFs thing.

-- 
You are receiving this mail because:
You are on the CC list for the bug.