[Libre-soc-bugs] [Bug 199] Layout using coriolis2 main core, 180nm

[bugzilla-daemon at libre-soc.org]

https://bugs.libre-soc.org/show_bug.cgi?id=199

--- Comment #69 from Luke Kenneth Casson Leighton <lkcl at lkcl.net> ---
(In reply to Jean-Paul.Chaput from comment #68)
> (In reply to Luke Kenneth Casson Leighton from comment #67)
> > (In reply to Jean-Paul.Chaput from comment #66)
> > > I did implement it in alliance-check-toolkit commit 76c4f45 and modificated
> > > experiment9 accordingly in commit c362610. I stick to the list approach.
> > 
> > star.  i will recompile and see how it goes.
> > 
> > > 
> > > It seems complicated to me to guess that list automatically. I think it
> > > should be done at nMignen level, as only the designer know where to stop.
> > 
> > ah sadly, nmigen itself quite "dumb".  its job is "take AST, turn it into
> > yosys ilang file".
> > 
> > that's *literally* it (!).
> > 
> > now... what i _could_ do is, from the original python class hierarchy, get
> > it to auto-generate a yosys script, that would work, hmmm.
> 
>   I'm not familiar with nMigen, but can't you put print statements
>   when instanciating a model/class just to fill the flatten file?

not at all!  it is literally, "call this function, it outputs a yosys ilang
file"

the order in which the modules are added is particularly involved.

i may need to create an Abstract Syntax Tree walker to get the names.

it should not be too hard.



> 
>   By the way, the loop is still there (will investigate after the
>   buffering is ok). You may notice that a *lot* of buffer is used.
>   It is a general trend as wires becomes longer and longer in SoCs.
>   And I still need to also bufferise long wires. So the result is
>   that more segments gets unrouteds (about 50).

ahh i wondered about buffering.

i apologise because this design, because it is intended to be multi issue
out-of-order, there are as you have seen *10* different execution engines, and
*17* integer register file fan-out for reading!

also when we have the Dependency Matrices, although only 1 bit will be driven,
there coukd be up to 40 DFFs (or SR NAND latches) on a single row.

only one of those will change HI/LO on any one clock cycle but it is still a
lot of things to drive from one source.

just so you know in advance and are not so freaked out :)

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