[Libre-soc-bugs] [Bug 199] Layout using coriolis2 main core, 180nm

[bugzilla-daemon at libre-soc.org]

https://bugs.libre-soc.org/show_bug.cgi?id=199

--- Comment #68 from Jean-Paul.Chaput at lip6.fr ---
(In reply to Luke Kenneth Casson Leighton from comment #67)
> (In reply to Jean-Paul.Chaput from comment #66)
> > I did implement it in alliance-check-toolkit commit 76c4f45 and modificated
> > experiment9 accordingly in commit c362610. I stick to the list approach.
> 
> star.  i will recompile and see how it goes.
> 
> > 
> > It seems complicated to me to guess that list automatically. I think it
> > should be done at nMignen level, as only the designer know where to stop.
> 
> ah sadly, nmigen itself quite "dumb".  its job is "take AST, turn it into
> yosys ilang file".
> 
> that's *literally* it (!).
> 
> now... what i _could_ do is, from the original python class hierarchy, get
> it to auto-generate a yosys script, that would work, hmmm.

  I'm not familiar with nMigen, but can't you put print statements
  when instanciating a model/class just to fill the flatten file?

  By the way, the loop is still there (will investigate after the
  buffering is ok). You may notice that a *lot* of buffer is used.
  It is a general trend as wires becomes longer and longer in SoCs.
  And I still need to also bufferise long wires. So the result is
  that more segments gets unrouteds (about 50).

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