[Libre-soc-bugs] [Bug 199] Layout using coriolis2 main core, 180nm

[bugzilla-daemon at libre-soc.org]

https://bugs.libre-soc.org/show_bug.cgi?id=199

--- Comment #67 from Luke Kenneth Casson Leighton <lkcl at lkcl.net> ---
(In reply to Jean-Paul.Chaput from comment #66)
> I did implement it in alliance-check-toolkit commit 76c4f45 and modificated
> experiment9 accordingly in commit c362610. I stick to the list approach.

star.  i will recompile and see how it goes.

> 
> It seems complicated to me to guess that list automatically. I think it
> should be done at nMignen level, as only the designer know where to stop.

ah sadly, nmigen itself quite "dumb".  its job is "take AST, turn it into
yosys ilang file".

that's *literally* it (!).

now... what i _could_ do is, from the original python class hierarchy, get it
to auto-generate a yosys script, that would work, hmmm.

then after the ilang file is generated, run a command to create the yosys
script then post-process it.

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