[Libre-soc-bugs] [Bug 490] Complete peripheral set including litex for first functional POWER9 Core

[bugzilla-daemon at libre-soc.org]

https://bugs.libre-soc.org/show_bug.cgi?id=490

--- Comment #9 from Luke Kenneth Casson Leighton <lkcl at lkcl.net> ---
hm.  litex is generating the following verilog:

module ls180(
    input wire [15:0] gpio,
);

wire [15:0] main_pads;
wire main_tstriple0_o;
wire main_tstriple0_oe;

assign main_pads[0] = main_tstriple0_oe ? main_tstriple0_o : 1'bz;
assign main_tstriple0_i = main_pads[0];


all of which looks dodgy to me.  gpio is an input only, for a start.
plus, i would kinda expect that those 3 _o, _oe and _i would be
"externally exposed" so you could connect them up manually.

don't know.  am putting it back to 8-in 8-out for now.

-- 
You are receiving this mail because:
You are on the CC list for the bug.