[Libre-soc-bugs] [Bug 490] Complete peripheral set including litex for first functional POWER9 Core

[bugzilla-daemon at libre-soc.org]

https://bugs.libre-soc.org/show_bug.cgi?id=490

--- Comment #10 from Luke Kenneth Casson Leighton <lkcl at lkcl.net> ---
running into yosys massive amounts of memory issues (12GB)

<daveshah> The solution will either to have LiteX use memory compiler
primitives instead; or remove all calls to memory_map in your Yosys script so
you are left with $mem cells (less ideal but maybe you can use memory_bram to
map them to your ASIC primitives)

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