[Libre-soc-bugs] [Bug 517] Define JTAG pins and set up with litex for ulx3s85f

[bugzilla-daemon at libre-soc.org]

https://bugs.libre-soc.org/show_bug.cgi?id=517

--- Comment #29 from Cole Poirier <colepoirier at gmail.com> ---
```proposed FPGA External Pin to STLINK JTAG pin connecitons
    pin #  | label # | FPGA IO PAD | GPIO # (n/p) | JTAG Pin # (Signal)  |
 1         |  3.3v   |    NONE     |     3v3      |      1 (MCU VDD)     |
 2         |  3.3v   |    NONE     |     3v3      |      2 (MCU VDD)     |
 3         | -|(GND) |    NONE     |     GND      |      3 (JNTRST)      |
 4         | -|(GND) |    NONE     |     GND      |      4 (GND)         |
 5 (J1_5-) |    0    |     C11     |    gn[0]     |      5 (JTDI)        |
 6 (J1_5+) |    0    |     B11     |    gp[0]     |      7 (JTMS)        |
 7 (J1_7-) |    1    |     A11     |    gn[1]     |      9 (JTCK)        |
 8 (J1_7+) |    1    |     A10     |    gp[1]     |     13 (JTDO)        |
 9 (J1_9-) |    2    |     B10     |    gn[2]     |       NONE           |
10 (J1_9+) |    2    |     A9      |    gp[2]     |       NONE           |
```

```proposed nmigen in litex/florent/versa_ecp5.py
gpio0    = self.platform.request("gpio", 0)
gpio1    = self.platform.request("gpio", 1)


jtag_tdi = gpio0.n
jtag_tms = gpio0.p
jtag_tck = gpio1.n
jtag_tdo = gpio1.p

# wire the pins up to CPU JTAG
self.comb += self.cpu.jtag_tdi.eq(jtag_tdi)
self.comb += self.cpu.jtag_tms.eq(jtag_tms)
self.comb += self.cpu.jtag_tdi.eq(jtag_tdi)
self.comb += jtag_tdo.eq(self.cpu.jtag_tdo)
```

Hi Luke, here is my plan for the physical connecting of the FPGA gpio pins to
the STLINK JTAG pins, and the nmigen code to initialize these selected gpio
pins as the 4 necessary JTAG pins. Can you approve this?

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