[Libre-soc-bugs] [Bug 519] Get output from ulx3s serial port to show up in minicom

[bugzilla-daemon at libre-soc.org]

https://bugs.libre-soc.org/show_bug.cgi?id=519

--- Comment #7 from Cole Poirier <colepoirier at gmail.com> ---
Created attachment 109
  --> https://bugs.libre-soc.org/attachment.cgi?id=109&action=edit
Patch that adds ability to build using versa_ecp5.py with ulx3s

Hi Luke, I needed to change a couple of things in order to get this to work.
For example I had to add the command line option --variant in
litex/florent/sim.py and remove the hard-coded cpu_data_width, but I think this
is actually what you wanted. i.e. replacing hard coded compilation options with
commandline options for the same. I've tested it and it runs the simulation,
builds successfully for ulx3s85f and successfully loads onto my ulx3s85f fpga.
Additionally, I tested that it builds successfully for versa_ecp5 but I
obviously can't test that it loads successfully as I don't have one. Let me
know what changes are necessary and I'll do another 'cycle' of this, then come
back here for approval to commit, or if it's correct now then let me know that
too :)

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