[Libre-soc-bugs] [Bug 502] determine SRAM block size and implement it

[bugzilla-daemon at libre-soc.org]

https://bugs.libre-soc.org/show_bug.cgi?id=502

--- Comment #4 from Luke Kenneth Casson Leighton <lkcl at lkcl.net> ---
(In reply to Staf Verhaegen from comment #2)

> The SRAM will have 1 port that can be used both for read or write with the
> following ports:
> - a: input of 7 bit
> - d: input of 64 bit
> - q: output of 64 bit
> - we: input of 8 bit
> - clk: input of 1 bit
> 
> The we vector input will determine for each byte (e.g. 8bits) if it is
> written or read.

ok that sounds great.  it matches with the above, i believe.

> Suppose we do an operation with 0x000000000000000 stored in an address and
> with d equal to 0xFFFFFFFFFFFFFFFF and we equal to 0xF0. After the operation
> the address will contain 0xFFFFFFFF00000000 and the Q output will also be
> 0xFFFFFFFF00000000.

address will contain 0xFFFFFFFF00000000? did you mean data in... oh, you
mean that data *at* the address.


(In reply to Staf Verhaegen from comment #3)

> I think you should estimate the maximum number of blocks you want to put on
> the design this way and confirm this then with Jean-Paul for P&R.

it should only be 9 (or so)

* 1x at address 0x0000_0000 for internal SRAM
* 4x for I-cache (4 "ways")
* 4x for D-cache (4 "ways")

yes only 4k I-cache and 4k D-cache.  (if we do need to expand that to 8k i will
do 2x 1k SRAMs and route "manually" using bit 8 of the address).

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