[Libre-soc-bugs] [Bug 506] 8x VDD VSS pins needed in ioring

[bugzilla-daemon at libre-soc.org]

https://bugs.libre-soc.org/show_bug.cgi?id=506

--- Comment #7 from Luke Kenneth Casson Leighton <lkcl at lkcl.net> ---
(In reply to Jean-Paul.Chaput from comment #6)
> (In reply to Luke Kenneth Casson Leighton from comment #5)
> 
> I will divert two or three days to make the port of the chip/corona
> plugin and the implementation of the new features. Would it be
> possible to have a shrunk down core but still with all the
> different I/O domains.

done.  lvx and cougar still take a massive amount of time despite there
being literally only one cell in the 9000x9000 lambda area, however i have
found that they can be interrupted (they are non-essential)

i have updated build.sh for you.

my thoughts overnight here are that clock and voltage domains should be part of
the ioring.py "chip" dictionary.

chip = {'chip.domains': {'SDRAM': ['p_list', 'of', 'iopads', 'for', 'sdram'],
                         'JTAG': ['p_list', 'of', 'jtag', 'pads']
                        },
        'chip.clocks': {'SDRAM': 'p_sdram_clock',
                        'JTAG': 'p_jtag_tck'
                        },
       }

and leave env.setCLOCK(), env.setPOWER() and env.setGROUND() alone
(do not modify) using them to specify "defaults"

the above dictionary format *should* be enough information to determine
the nets, by parsing the chip['pads.instances'] and pads.south/east/n/w
information.

IoPadConf contains the "lookup" information to turn p_xxx_xxx into NETs,
particularly for the _i, _o and _oe net names.

what do you think, jean-paul?

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