[Libre-soc-bugs] [Bug 507] ls180 asic needs an ioring, pads need defining and connecting

[bugzilla-daemon at libre-soc.org]

https://bugs.libre-soc.org/show_bug.cgi?id=507

--- Comment #9 from Luke Kenneth Casson Leighton <lkcl at lkcl.net> ---
(In reply to Luke Kenneth Casson Leighton from comment #8)

> hm i must make a dummy PLL for you with an input of "sys_clk" and an output
> "internal_pll_clk" i will do that before afternoon.

this is now done, it is:

* sys_clk input from ioring thru corona
* sys_clk connects to "dummy" PLL
* pll_out connects to clksel module
* clksel outputs "core" (internal) clock
* core clock drives most of ls180

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