[Libre-soc-bugs] [Bug 507] ls180 asic needs an ioring, pads need defining and connecting

[bugzilla-daemon at libre-soc.org]

https://bugs.libre-soc.org/show_bug.cgi?id=507

--- Comment #8 from Luke Kenneth Casson Leighton <lkcl at lkcl.net> ---
(In reply to Jean-Paul.Chaput from comment #7)
> (In reply to Luke Kenneth Casson Leighton from comment #6)
> Have meetings this afternoon, works on it right after.

ok i leave this with you for after meeting.

for the dictionary spec, env.SETCLOCK could take an example:

env.setCLOCK({'default': '^internal_pll_clk$',
          'jtag_pck': ['jtag_tms', 'jtag_tdo', 'jtag_tdi'],
          'sys_clk': [], # TODO
          'sd0_clk': ['sd0_cmd_i', "sd0_cmd_o", "sd0_cmd_oe",
                 'sd0_data_i', "sd0_data_o", "sd0_data_oe",
       "sdram_clock": "^sdram_.*"
         })

notes:

* any IOPad (corona) signal not in any list or patternmatch uses "default"
* each of these pck_px rings is completely independent!
* notice that sys_clk the external 24 mhz is not the default!

this would get you started while i generate the "real" one.

hm i must make a dummy PLL for you with an input of "sys_clk" and an output
"internal_pll_clk" i will do that before afternoon.

-- 
You are receiving this mail because:
You are on the CC list for the bug.