[Libre-soc-bugs] [Bug 506] 8x VDD VSS pins needed in ioring

[bugzilla-daemon at libre-soc.org]

https://bugs.libre-soc.org/show_bug.cgi?id=506

Staf Verhaegen <staf at fibraservi.eu> changed:

           What    |Removed                     |Added
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                 CC|                            |staf at fibraservi.eu

--- Comment #4 from Staf Verhaegen <staf at fibraservi.eu> ---
Actually for the 0.18um tape-out the core voltage will be 1.8V and the IO
voltage 3.3v. So separate supply have to also be foreseen for the VDDIO and
VSSIO. Let's also take 2 VDDIO/VSSIO pairs on each side for the moment. This
may be reduced in the future to one pair on each side.

To reduce bond wire loop area it is also best to put the VDD/VSS pins next to
each other in the IO-ring.

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