[Libre-soc-bugs] [Bug 199] Layout using coriolis2 main core, 180nm

[bugzilla-daemon at libre-soc.org]

https://bugs.libre-soc.org/show_bug.cgi?id=199

--- Comment #5 from Luke Kenneth Casson Leighton <lkcl at lkcl.net> ---
(In reply to Jean-Paul.Chaput from comment #4)
> Coriolis commit b48f9b4 fixes:
> 
> * soclayout/experiments6, we can generate the fpmul64 example without
>   using Yosys flatten, the vst should now be correct. The synthesis
>   gives ~21K gates and the P&R takes a little above 3 minutes.
>   So perfectly manageable.

fantastic.

> 
> * soclayout/experiment9, invalid syntax in port map (no right hand
>   signal...).

hmmm... will take a look later, am in the middle of sorting out other
memory-bus stuff.

> Additional commit f3dd4bc fixes:
> 
> * Incomplete hierarchical save (Cumulus rsave plugin).
> 
> About the size of test_issuer:
> 
> It appears that most of the cells are in the "mem" module, that is
> 93% of them (for a total of 844321). It seems wrong to me.

yep, it is initialised with 262144 bits.  that means that somewhere the "mem"
instance is being passed an address range of (1<<18) where it should only be
around 1<<6 for these purposes.

i'll take a look now.

l.

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