[Libre-soc-bugs] [Bug 199] Layout using coriolis2 main core, 180nm

[bugzilla-daemon at libre-soc.org]

https://bugs.libre-soc.org/show_bug.cgi?id=199

--- Comment #4 from Jean-Paul.Chaput at lip6.fr ---
Coriolis commit b48f9b4 fixes:

* soclayout/experiments6, we can generate the fpmul64 example without
  using Yosys flatten, the vst should now be correct. The synthesis
  gives ~21K gates and the P&R takes a little above 3 minutes.
  So perfectly manageable.

* soclayout/experiment9, invalid syntax in port map (no right hand
  signal...).

Additional commit f3dd4bc fixes:

* Incomplete hierarchical save (Cumulus rsave plugin).

About the size of test_issuer:

It appears that most of the cells are in the "mem" module, that is
93% of them (for a total of 844321). It seems wrong to me.
IMHO, two possibilities here:

1. The real complexity of the "mem" module was drastically
   underestimated.

2. The way the nMignen code of "mem" is written trick Yosys in
   doing very unoptimzed things.

Note that with such an unbalance in the size of the modules / FU,
a realistic placement makes little sense.

Anyway, I strongly suggest a review of that module to, at least,
understand and justify such a size.

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