[Libre-soc-bugs] [Bug 393] Hook up augmented-Wishbone Memory Bus to LDSTCompUnit (via PortInterface)

[bugzilla-daemon at libre-soc.org]

https://bugs.libre-soc.org/show_bug.cgi?id=393

--- Comment #19 from Luke Kenneth Casson Leighton <lkcl at lkcl.net> ---
i've created TestMemoryPortInterface:
https://git.libre-soc.org/?p=soc.git;a=blob;f=src/soc/experiment/pimem.py;hb=HEAD

it's based *on* L0CacheBuffer however is simpler in that it "manages"
the TestMemory itself.

i've added comments into TestMemoryPortInterface that it is intended as the
"absolute simplest compliant thing with PortInterface that can handle
LOAD/STOREs"

L0CacheBuffer now basically reduces to the role of "PortInterface Arbiter",
picking one and only one incoming PortInterface and passing it through.

that's the next task.

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