[Libre-soc-bugs] [Bug 393] Hook up augmented-Wishbone Memory Bus to LDSTCompUnit (via PortInterface)

[bugzilla-daemon at libre-soc.org]

https://bugs.libre-soc.org/show_bug.cgi?id=393

Luke Kenneth Casson Leighton <lkcl at lkcl.net> changed:

           What    |Removed                     |Added
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           Assignee|yimmanuel3 at gatech.edu       |mtnolan2640 at gmail.com
         Depends on|                            |403

--- Comment #20 from Luke Kenneth Casson Leighton <lkcl at lkcl.net> ---
(In reply to Luke Kenneth Casson Leighton from comment #19)

> L0CacheBuffer now basically reduces to the role of "PortInterface Arbiter",
> picking one and only one incoming PortInterface and passing it through.
> 
> that's the next task.

done.  L0CacheBuffer's sole job now is to select between incoming
PortInterfaces (one per LDSTCompUnit), and to output *to* a PortInterface.

that will however not provide support for misaligned requests.

however the nice thing is: DualPortSplitter *will* deal with misaligned
requests... and DualPortSplitter is intended to comply with PortInterface.

hook one up to the other...


Referenced Bugs:

https://bugs.libre-soc.org/show_bug.cgi?id=403
[Bug 403] runtime configureable LoadStoreUnit needed
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