[Libre-soc-bugs] [Bug 393] Hook up augmented-Wishbone Memory Bus to LDSTCompUnit (via PortInterface)

[bugzilla-daemon at libre-soc.org]

https://bugs.libre-soc.org/show_bug.cgi?id=393

Luke Kenneth Casson Leighton <lkcl at lkcl.net> changed:

           What    |Removed                     |Added
----------------------------------------------------------------------------
            Summary|Hook up L2 Cache to         |Hook up augmented-Wishbone
                   |Wishbone/LDST Wrappers      |Memory Bus to LDSTCompUnit
                   |                            |(via PortInterface)

-- 
You are receiving this mail because:
You are on the CC list for the bug.