[Libre-soc-bugs] [Bug 325] create POWER9 TRAP pipeline

[bugzilla-daemon at libre-soc.org]

https://bugs.libre-soc.org/show_bug.cgi?id=325

--- Comment #98 from Cole Poirier <colepoirier at gmail.com> ---
(In reply to Luke Kenneth Casson Leighton from comment #97)
> (In reply to Cole Poirier from comment #95)
> 
> > 
> > Ah yes saw that, I meant how I should set it in the code I write for
> > caller.py
> 
> well, as i am guessing as much as anyone, here, given that nothing has been
> tested i'd suggest just going with it and adapting iteratively.
> 
> starting by running a tdi instruction in test_sim.py and seeing what
> happens, checking whether the PC changes to 0x700 or not.

I meant, don't I have to compare against TO and set the correct bit for the
TRAP exception type? How to implement the following in caller.py:
(comment #1 of this bug report)
```
if (a < b) & TO[0] then TRAP
if (a > b) & TO[1] then TRAP
if (a = b) & TO[2] then TRAP
if (a <u b) & TO[3] then TRAP
if (a >u b) & TO[4] then TRAP
```

and the related:
```
PI_FP   = (63 - 43)    # 1 if FP exception
PI_PRIV = (63 - 45)    # 1 if privileged interrupt
PI_TRAP = (63 - 46)    # 1 if exception is "trap" type
PI_ADR  = (63 - 47)    # 0 if SRR0 = address of instruction causing            
exception
```

Do I just set the appropriate bit in SRR1? And I do this after setting SRR1 to
the old MSR? Or I set MSR to (?) with the appropriate bit for the TRAP
exception set?

Right now comment #3 and the code you wrote for fu/trap/main_stage.py's 
`with m.Case(InternalOp.OP_TRAP):` section seem to conflict. Perhaps I'm just
not getting it, but it does seem like there's an inconsistency that needs to be
resolved. 

(comment #3 of this bug report)
```
section 7.5.9 covers TRAP, and shows that yes:

* SRR0 is set to "PC following trap"
* SRR1 contains the *old* MSR (sorry, not the new MSR)
* MSR is updated to meet the conditions of the trap
```
fu/trap/main_stage.py's 
`with m.Case(InternalOp.OP_TRAP):`
```
#### trap ####
with m.Case(InternalOp.OP_TRAP):
    # trap instructions (tw, twi, td, tdi)
    with m.If(should_trap):
        # generate trap-type program interrupt
        self.trap(trapaddr<<4, cia_i)
        with m.If(traptype == 0):
            # say trap occurred (see 3.0B Book III 7.5.9)
            comb += srr1_o.data[PI_TRAP].eq(1)
        with m.If(traptype & TT_PRIV):
            comb += srr1_o.data[PI_PRIV].eq(1)
        with m.If(traptype & TT_FP):
            comb += srr1_o.data[PI_FP].eq(1)
        with m.If(traptype & TT_ADDR):
            comb += srr1_o.data[PI_ADDR].eq(1)
```

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