[Libre-soc-bugs] [Bug 325] create POWER9 TRAP pipeline

[bugzilla-daemon at libre-soc.org]

https://bugs.libre-soc.org/show_bug.cgi?id=325

--- Comment #99 from Luke Kenneth Casson Leighton <lkcl at lkcl.net> ---
(In reply to Cole Poirier from comment #98)


> I meant, don't I have to compare against TO and set the correct bit for the
> TRAP exception type? How to implement the following in caller.py:

look in fixedtrap.py.  search for op_tdi.  does it not look familiar?

> (comment #1 of this bug report)
> ```
> if (a < b) & TO[0] then TRAP
> if (a > b) & TO[1] then TRAP
> if (a = b) & TO[2] then TRAP
> if (a <u b) & TO[3] then TRAP
> if (a >u b) & TO[4] then TRAP
> ```

does op_tdi etc not look like that?

> and the related:
> ```
> PI_FP   = (63 - 43)    # 1 if FP exception
> PI_PRIV = (63 - 45)    # 1 if privileged interrupt
> PI_TRAP = (63 - 46)    # 1 if exception is "trap" type
> PI_ADR  = (63 - 47)    # 0 if SRR0 = address of instruction causing         
> exception
> ```

ok you miiight simply be able to import thise and use them.

although strictly speaking they ahoukd be moved to a common location.

> Do I just set the appropriate bit in SRR1? And I do this after setting SRR1
> to the old MSR? Or I set MSR to (?) with the appropriate bit for the TRAP
> exception set?

i don't know! like i said i would simply try it and check SRR1 (etc) in
test_sim.py alongside testing of PC.

then if the test fails you have the beginnings of a comparative answer.

tests failing *is* ok.

just go with it.

write the unit test.

run it.

stop flapping about, worrying about what you don't know: write the darn test
and run it already! :)

i know what is going on.  you are false correlating "i don't know what i am
doing" with "i should not take action UNTIL.i know what i am doing".

this will get you precisely nowhere.

by setting up an iterative loop (based around the unit test) you can make
progress *despite* not knowing.

write the darn test and run it! :)

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