[Libre-soc-bugs] [Bug 325] create POWER9 TRAP pipeline

[bugzilla-daemon at libre-soc.org]

https://bugs.libre-soc.org/show_bug.cgi?id=325

--- Comment #97 from Luke Kenneth Casson Leighton <lkcl at lkcl.net> ---
(In reply to Cole Poirier from comment #95)

> 
> Ah yes saw that, I meant how I should set it in the code I write for
> caller.py

well, as i am guessing as much as anyone, here, given that nothing has been
tested i'd suggest just going with it and adapting iteratively.

starting by running a tdi instruction in test_sim.py and seeing what happens,
checking whether the PC changes to 0x700 or not.

-- 
You are receiving this mail because:
You are on the CC list for the bug.