[Libre-soc-bugs] [Bug 397] design and discuss user-tag flags in wishbone to provide phase 1 / 2 "speculative" memory accesses

[bugzilla-daemon at libre-soc.org]

https://bugs.libre-soc.org/show_bug.cgi?id=397

--- Comment #5 from Luke Kenneth Casson Leighton <lkcl at lkcl.net> ---
i'm reading the wb4 spec and table in section 3.1.6 shows the 4 types of
userdefined signals permitted to ne added.  ir, more to the pount, if added
rgey must be "tagged" in the datasheet and must also respect the timing
protocol associated with that tag.

however none of these 4 tag types perfectly fit the "shadow" system aka
"standard contract of sale".

we may have to do this:

* define a "cycle" tagged signal that indicates that the bus is to follow
"shadow" protocol.  this is raised and geld for the whole CYC_O

* at that point, the slave can assume that all operations are implicitly under
"shadow" conditions and that it must wait for "success or fail".

* the address will be sent as normal for a read

* however the slave MUST wait for the master to raise a DATAO tag (despite this
being a read) of EITHER success or fail (GO_DIE).

i am inclined to recommend that the slave be required to raise STALL_I at this
point, until either success or fail is raised.

btw that fail is synonymous with RST.  it is the same thing.  however i do not
know at this point if is a bit drastic to do a full RST.

alternatively we could simply specify that if cyc is dropped when STALL_I is
raised this is equivalent to "GO_DIE".

success on the other hand is simple enough. 

remember - irritatingly - we cannot pass shadow itself through because it does
not fit *any* of the 4 tag types.

unless of course we simply define that it is permitted to be.

this would be easier and fit better.

more thought required.

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