[Libre-soc-bugs] [Bug 397] design and discuss user-tag flags in wishbone to provide phase 1 / 2 "speculative" memory accesses

[bugzilla-daemon at libre-soc.org]

https://bugs.libre-soc.org/show_bug.cgi?id=397

--- Comment #6 from Luke Kenneth Casson Leighton <lkcl at lkcl.net> ---
right.  another thought occurred to me.

1. peripherals have to be done as "take it or leave it" style wishbone access.

2. main memory (DRAM) also falls onto this category.  note: that's not *cached*
memory, it's *actual* memory (via SDRAM wishbone controller or LiteDRAM etc)

3. it is only the *processor* that needs to perform these speculative style
"house contract of sale" requests.

4. therefore we *are* actually free and at liberty to design and use an
internal bus architecture, which L0, L1, L2 and TLB and MMU understand, that
respects the "house contract of sale" interface, this being an internal
protocol.

5. however when interfacing to *peripherals* we must treat them as atomic and
can use the take-it-or-leave-it protocol, falling back to single blocking
operations and thus safely use wishbone.

6. as far as memory (DRAM) is concerned, as long as *batches* are respected
(batches of LD requests that do not overlap with batches of STs) and once we
have determined that the addresses of all batches are valid these LD-only or
ST-only can be done in any order at any width.

in addition: given that we are only doing  a single core we have only one
access route to memory to worry about.

we are also not going to put VM in... yet.

now, the discerning factor which tells us the difference between memory and
peripherals is: the address.

and it is the address that we need to check first at the "house contract Phase
1".

this is incredibly simple:

* is address in range of real DRAM, yes or no.  if yes, we ASSUME, reasonably,
that when it proceeds to Phase 2 it will succeed.

after that point we *CAN* in fact use minerva for accessing DRAM because it is
guaranteed to succeed.  errors however are promoted to "catastrophic".

for peripherals, these fall back to atomic blocking operations so we can
*still* use minerva LoadStoreInterface however errors are straight exceptions
rather than catastrophic.

for peripherals the L1 cache must also be bypassed because you have to actually
do the read and actually do the write.  this is slow and is what DMA is for,
but hey.

-- 
You are receiving this mail because:
You are on the CC list for the bug.