[Libre-soc-bugs] [Bug 397] design and discuss user-tag flags in wishbone to provide phase 1 / 2 "speculative" memory accesses

[bugzilla-daemon at libre-soc.org]

https://bugs.libre-soc.org/show_bug.cgi?id=397

--- Comment #4 from Luke Kenneth Casson Leighton <lkcl at lkcl.net> ---
(In reply to Jacob Lifshay from comment #2)
> (In reply to Luke Kenneth Casson Leighton from comment #0)
> > the requirements are - and this is not optional - that memory requests be
> > subdivided into two phases:
> > 
> > 1) checking whether the request *CAN* be completed - WITHOUT EXCEPTIONS - if
> >    it were to be permitted to proceed
> > 
> > 2) allowing the memory request to proceed.
> 
> There are some peripherals where they only error after proceeding to the
> point where it's impossible to cancel a request, so, our memory request
> state diagram needs to properly handle that, without just hard-locking the
> CPU or creating an inprecise interrupt.

yes.  POWER architecture recognises that these peripherals exist, and puts
them into the "atomic" category.  there's a section on them, somewhere.

this in turn holds up (entirely) all subsequently-issued LD/STs even from
exiting anything beyond the "GO_ADDR" phase (the computation of the
Effective Address).


> This would involve waiting until non-speculative for non-cachable memory
> addresses and potentially serializing operations.

correct.  once the (effectively atomic) LD/ST had proceeded past its
"take-it-or-leave-it" contract, further "speculative" contracts may
proceed in parallel.

(see https://libre-soc.org/3d_gpu/architecture/6600scoreboard/discussion/
for explanation of the contract terminology)

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