[Libre-soc-bugs] [Bug 382] nmigen wishbone Memory (SRAM) object needed

[bugzilla-daemon at libre-soc.org]

https://bugs.libre-soc.org/show_bug.cgi?id=382

--- Comment #13 from Yehowshua <yimmanuel3 at gatech.edu> ---
Basically this is the cache interface that I tried to do around Minerva's
cache,
but its really really hard to shoehorn Minerva's two stage cache.

(Higher Memory or CPU) <==> (CACHE) <==> (Lower Memory or RAM)

I'm going to start writing such a cache and its proof.
I could have finished it in the time I spent trying to shoehorn Minerva.
It will be useful for my thesis, hopefully it will make sense for LibreSOC.

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