[Libre-soc-bugs] [Bug 382] nmigen wishbone Memory (SRAM) object needed

[bugzilla-daemon at libre-soc.org]

https://bugs.libre-soc.org/show_bug.cgi?id=382

--- Comment #12 from Yehowshua <yimmanuel3 at gatech.edu> ---
(In reply to Yehowshua from comment #11)
> In fact, Minerva's cache codebase is really bizarre.
> We'd really have to shoe horn it I think.

Basically, any time there is a write, if the entry is in the cache,
it gets evicted from the cache.

The write data then goes around the cache - not through the cache,
on a separate bus, directly to memory.

Yehowshua

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